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October 15, 2003
Transmeta's Efficeon Challenges Pentium M for Slimline Notebook Supremacy
Crusoe Successor Combines CPU and Northbridge

Systems based on it aren't expected to ship until the fourth quarter, but Transmeta Corp. took the wraps off its Efficeon processor at this week's Microprocessor Forum in San Jose, Calif. Successor to Transmeta's Crusoe CPU, the Efficeon is designed to outperform competing chips in high-performance, low-power x86 environments such as ultralight notebooks, Tablet PCs, blade servers, and silent (fanless) desktops.

Debuting at 1.1GHz with 192K of Level 1 (128K for instructions, 64K for data) and 1MB of Level 2 cache, the Efficeon TM8600 features a new silicon microarchitecture -- based on a 256-bit Very Long Instruction Word (VLIW) processor that can issue up to eight internal instructions per clock cycle, twice as many as Crusoe -- and new version of Transmeta's Code Morphing software, compatible with MMX, SSE, and SSE2 multimedia instructions.

Not only a high-speed DDR400 memory interface (with ECC support), but an AGP 4X graphics interface is built into the CPU, eliminating the need for a separate Northbridge chip. A 1.6GB/sec HyperTransport interconnect communicates with the rest of the system, offering up to 12 times the I/O throughput of Crusoe's PCI interface. A high-speed LPC (Low Pin Count) bus communicates with the latest generation of flash memory.

The Efficeon TM8600 package measures just 29mm square, while a special TM8620 version is only 21mm square; pairing the latter with Nvidia's new 22mm-square nForce3 Go 120 Southbridge, Transmeta says, yields a combination of CPU, Northbridge, and Southbridge in a space nearly four times smaller than its nearest competitor. The nForce3 Go 120 provides 10/100Mbps Ethernet, 6-channel AC97 audio with S/PDIF digital output, and PCI, ATA/133, and USB 1.1 and 2.0 interfaces.

While the first Efficeon processors are built with TSMC's 0.13-micron CMOS technology, the second half of 2004 will see 90-nanometer-process versions manufactured by Fujitsu. Transmeta hints that these CPUs will include a new LongRun2 version of its power management technology, which the company says can control the transistor leakage that accounts for an increasing percentage of total chip power and heat as processors scale from 0.13 micron to 90nm and in the future 65nm. LongRun2 uses software to adjust not only megahertz and voltage but transistor leakage dynamically, up to hundreds of times per second, based on application demand.

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