UltraSparc IV+ Adds L2 Cache, Efficeon Whittles Away Wattage

What’s more in fashion than the miniskirt? The die shrink, as other CPU makers follow Intel and AMD in moving their manufacturing from 0.13-micron to 90-nanometer-process technology. At this week’s In-Stat/MDR Fall Processor Forum in San Jose, Calif., Transmeta Corp. released more details of the 90-nanometer version of its Efficeon chip for slimline notebooks, blade servers, and fanless media centers, while Sun Microsystems Inc. unveiled the 90-nanometer successor to today’s UltraSparc IV dual-core server CPU.

The Efficeon TM8800 integrates Northbridge chipset functionality including a DDR400 memory controller and AGP 4X graphics interface, as well as featuring what Transmeta calls AntiVirusNX technology — the Data Execution Protection feature that debuted in Microsoft’s Windows XP Service Pack 2. While the 0.13-micron Efficeon TM8600 achieved 1.0GHz speeds at a maximum power of 7 watts, the TM8800 is expected to deliver the same performance using a measly 3 watts — and scale to higher speeds, with a 1.6GHz chip already in limited production and a 2.0GHz Efficeon demonstrated at the Fall Processor Forum.

Similarly, while Sun’s UltraSparc IV peaks at 1.2GHz, the 90-nanometer-process UltraSparc IV+ will debut at 1.8GHz, with roughly twice the per-thread performance and appliation throughput of the existing UltraSparc IV. Like that chip, it’s a 64-bit, dual-core design, but the new model boasts expanded caches and buffers, a better branch-prediction mechanism, augmented prefetch capabilities, and a new three-level cache hierarchy including an on-chip 2MB instead of its predecessor’s external 16MB Level 2 cache. The IV+ will have an off-chip Level 3 cache of 32MB.

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