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Kick It Down a Notch: Intel Builds 65-Nanometer-Process SRAMs August 31, 2004 Second-Generation Strained Silicon Already looking beyond today's 90-nanometer-process technology, Intel Corp. has built fully functional 70-megabit static random access memory (SRAM) chips using 65-nanometer process lithography. The silicon giant, which used the 65nm process to create prototype 4-megabit SRAMs last November, says it's on track to deliver 65-nanometer-process CPUs in 2005, with 45-nanometer lithography starting production in 2007 and 32-nanometer engineering in 2009. Each of the new SRAMs has more than half a billion transistors, with gates or on/off switches measuring 35 nanometers -- approximately 30 percent smaller than those of current 90-nanometer technology. Intel adds that about 100 such gates could fit inside the diameter of a human red blood cell, or that 10 million of the new transistors would occupy one square millimeter (think the tip of a ballpoint pen). The strained-silicon technology that Intel first implemented in its 90-nanometer process technology has been enhanced on the 65-nanometer assembly line, increasing transistor performance by 10 to 15 percent without increasing leakage (or matching the older transistors' performance with only one-quarter the leakage). This reduces heat generation as well as making physical room for more cache or dual processor cores on a die. In another high-efficiency measure, the 65nm SRAM implements "sleep transistors" that shut off the current flow when they're not being utilized, eliminating a significant source of power consumption.