Looking Beyond 90-Nanometer Processes
Ever since Intel chairman emeritus Gordon Moore predicted in 1965 that the number of transistors on (and hence the power of) a silicon chip would double every couple of years, Moore’s Law has depended on squeezing more transistors into a smaller space. For that to continue past the next few years, however, the channels that power the fastest CPUs will need to become smaller than the light wavelengths used to etch them into silicon.
This is possible, with an elaborate setup of masks and filters, but very tricky and expensive. As a result, microprocessor manufacturers are turning to new methods to get the most from their current tools and lay the groundwork for the next generation of lithographic tools, including what’s called Extreme Ultraviolet lithography (EUV) and possibly even submerged fabrication.
“No physical quantity can continue to change exponentially forever,” Moore told the crowd at the International Solid-State Circuits Conference in San Francisco in February. But Moore also said that chip vendors should be able to keep shrinking their wares for another decade at least by embracing these new technologies.
Traditional photolithography works a little like a slide projector, using ultraviolet light to imprint patterns on silicon chips. In current manufacturing processes, light is projected through a stencil onto a silicon wafer. The wafer is coated with a resist — a light-sensitive polymer that reacts with the light — and then etched with chemicals that remove either the exposed or unexposed polymer. After the wafer is washed to remove the excess, what remains is a minutely fine etched pattern that can channel electrons, sort of like a far larger array of physical wires.
Unfortunately, conventional photolithography methods are difficult and expensive. Weighing as much as 20 tons and costing up to $17 million apiece, lithography machines have pushed the total price of building a new 300mm chip fabrication facility past $2.5 billion.
As an earlier CPU Planet article noted, sales of such expensive gear have been hurt by the slowdown in the world economy and overall semiconductor market — although 2003 will mark a small recovery, with global sales of lithography tools projected to reach $4.3 billion, according to the Information Network, a research firm based in New Tripoli, N.Y.
More seriously, however, there are questions about the long-term sustainability of traditional technique. Intel’s Pentium 4 successor “Prescott” and other chips due from the state-of-the-art fabs coming online later this year use a 90-nanometer (0.09-micron) process, featuring even tinier (50-nanometer) transistors than those of today’s 0.13-micron-process CPUs. Such lithography devices use light wavelengths of 193 nanometers (billionths of a meter).
At this point, manufacturers are approaching the diffraction limit of light itself. It is very difficult to make channels that are smaller than the wavelength of light — yet to maintain the current trend of performance improvements, the Consortium of International Semiconductor Companies projects that transistors will have to be smaller than 9 nanometers by 2016. This forces manufacturers to search for alternative methods to keep Moore’s Law rolling.
Smaller Than the Speed of Light
Indeed, Intel recently announced that its next generation of lithography devices, designed to produce light at 157- rather than 193-nanometer wavelengths, will be delayed from 2005 to 2007 or later. (The news comes now because the chipmaker must choose a lithography platform 18 months ahead of full-scale production.) Intel blames the delay on both the economic slowdown and on wrestling with technical glitches such as an “intrinsic birefringence” problem with the calcium fluoride used in the machines.
The chipmaker had been planning to make the switch to 157-nanometer lithography tools in time for the next step after 90-nanometer manufacturing — the 65-nanometer process it plans to introduce in 2005. Instead, the company says it will extend 193-nanometer lithography to handle that process as well, using sophisticated phase-shift masks to adapt current machinery to build not only 65- but even 45-nanometer chips, which should take Intel safely through 2007.
To the Extreme
Intel has also pushed back its plans to deploy so-called Extreme Ultraviolet lithography (EUV) tools — to 2009, when the chipmaker’s product roadmap calls for 32-nanometer process manufacturing. Intel has not decided whether to use the forthcoming 157-nanometer or EUV tools to build such chips, but sources at the company say EUV has the better chance.
Extreme ultraviolet lithography was originally developed by the U.S. Department of Energy and Sandia National Labs, but its progress has since been taken over by a consortium of private-sector vendors including AMD and IBM as well as Intel. Though similar to today’s optical lithography, EUV uses light with light with wavelengths up to 10 times smaller — meaning it could create processors 10 times faster than today’s, with 10 times as many active transistors. If used to create memory chips, EUV could produce modules with 40 times today’s storage capacity.
Any EVU lithographic process will be complicated, because EUV light is easily diffracted. The challenge is to build mirrors perfect enough to reflect the light with sufficient precision. In fact, the air itself can absorb EUV light and cause production errors.
Lithography vendors themselves are uncertain about EUV possibilities, and looking for ways to hedge their bets. Companies like ASML Holding NV, Canon Inc., and Nikon Corp. are working to prolong the life of existing lithographic platforms — by getting them wet.
Immersion lithography inserts a layer of liquid (deionized water, cyclo-octane, or Krytox) between the projection lens and the wafer. This extra layer could permit finer resolutions than traditional lithography — according to proponents, extending 193-nanometer tools down to 45 nanometers and below. That would make immersion lithography a highly viable competitor to 157-nanometer and extreme ultraviolet tools.
Intel has pooh-poohed immersion lithography as unfeasible, but a few working prototypes exist. Engineers at RIT have built two 193-nanometer immersion scanners, albeit purely for research purposes, while Nikon claims it has used similar equipment to print 65-nanometer lines. Sematech is performing a study to see whether it’s practical to bring immersion techniques to the marketplace.
Something Besides Light at the End of the Tunnel?
Meanwhile, lithography isn’t the only way to make chips. Physicists at Princeton University are experimenting with a new method of imprinting silicon. The technique, called laser-assisted direct imprint, uses quartz molds to imprint silicon patterns with a resolution of 10 nanometers; the pattern is first cut into the mold, and then the latter is pressed into liquid silicon. This type of impact lithography could be much cheaper than conventional light-based methods, and because it doesn’t require resists and chemical washes, it could be faster as well.
Still, the world’s smallest transistor gate (at presstime, anyway) was created not only with current lithographic tools, but with relatively long 248-nanometer-wavelength lithography. IBM was able to build a working transistor gate measuring just 6 nanometers by using bonded silicon-on-insulator (SOI) wafers with halo implants.
Dr. Randy Isaac, vice president of science and technology for IBM Research, has said, “The ability to build working transistors at these dimensions could allow us to put 100 times more transistors into a computer chip than is currently possible. Moreover, this achievement underscores the fundamental challenges of scaling, namely power density, that must be addressed as silicon is pushed to molecular dimensions.”
Whatever the final arrival date of EVU and ultra-fine lithography tools, after 2010 or so, nanotechnology will start to take over — and lithography itself may be replaced with carbon nanotubes or molecular processors. But that is another story.